Abstarct: Quadrature voltage-controlled oscillators (QVCOs) are one of the most important building blocks of any high-frequency analog and digital communication systems. These oscillators are used in both the transmit and receive paths of the transmitter-receivers and their performance affects the overall system performance. Among the quadrature signal generation techniques, the quadrature LC oscillators have a better performance in term of phase noise and power consumption. These quadrature oscillators consist of two main parts: two identical core oscillators and a coupling network, which both of them play an effective role in phase noise and power consumption. However, one of the important challenges is trade-off between phase noise, power consumption and phase accuracy. In this thesis, a QVCO with current-reused structure is proposed to achieve low power consumption for application at 5.02 GHz frequency range. The proposed oscillator core consists of two NMOS and PMOS transistors and an additional NMOS-only cross-coupled pair that results in increase of effective transconductance and ease of the start-up condition. Therefore, the oscillator can operate with low current and results in reducing of power consumption. In the proposed coupling scheme, the gate of cross-coupled transistors is used for coupling, so no additional elements are required for coupling and the phase noise performance is improved. Parallel capacitors to the drain-source of transistors have been used to further increase the transconductance and thus reduce power consumption. On the other hand, the increase in parallel capacitors reduces the tuning range, indicating another trade off in the proposed QVCO. The proposed quadrature oscillator is designed and simulated using ADS software with TSMC 0.18μm RF-CMOS technology. The results of the simulation show that this structure has a power consumption of 1.2 mW at the supply voltage of 0.8 V and the phase noise of the QVCO at 1 MHz frequency offset from the 5.02 GHz is -123.1 dBc/Hz. The figure of merit (FOM) of the proposed circuit is -196.24 dBc.