Abstarct: Integrated circuit designers, along with the improvement of CMOS technology and the scale down of transistor dimensions and supply voltages are looking for low-power and high-speed operational amplifiers. Improving the slew rate without increasing the power consumption is one of the major challenges in amplifier design. Therefore, in this research, the slew rate and efficiency of the two-stage operational amplifiers discussed in the previous works, have been investigated. According to the presented structures in previous studies, a different structure to improve the slew rate of the two-stage single-ended operational amplifier has been proposed. The results of this study shows that the positive and negative slews in this two-stage single-ended Op Amp by using a new auxiliary monitor circuit, the QFG method on the second stage, changing the compensation type and for a load capacitor of 1 pF and supply voltage of 1.8 V in the TT process corner have increased 7.6 and 10 times respectively, compared to its conventional structure. The proposed auxiliary circuit in this structure causes to increase in the negative slew rate in the single-ended two-stage operational amplifier. The operating time of the auxiliary monitor circuit is very short. Therefore, the power consumption has increased only by 0.89 %. On the other hand, the auxiliary circuit has little effect on the gain, bandwidth and the phase margin of the operational amplifier and can be ignored. In this two-stage Op Amp, the indirect compensation is used that despite of Miller (direct) compensation, results in increase of bandwidth, reduce in the compensation capacitor size and having higher slew rate. The simulation results in ADS software using TSMC 0.18μm RF-CMOS technology at process corners of TT, FF, SS, SF and FS show that the auxiliary circuit at at process corners has acceptable performance. As a result, the proposed structure in this research, along with circuit simplicity and low power consumption, has been able to increase the positive and negative slew rates symmetrically. This structure has a gain of 69 dB, a phase margin of 72 deg, a frequency gain of 144 MHz and a symmetrical slew rate of 618 V/µs. Also, the power consumption of this circuit is 564 µW, which leads to having 1/1 competency factor.