Abstarct: Due to the high speed of technology development in the field of microelectronics, there is a need for high-speed devices and low power consumption. Designers are keen on designing and building new nano-sized devices. One of these technologies is QCA, which enables high-speed digital circuit implementations. The calculations in this technology are done by quantum dots and the unit forming the devices designed by this method is quantum cells. Quantum cells can design logical gates and quantum wires, as well as more complex structures such as RAM memory cells. Memory plays a role in the speed of computer systems and so far various implementations have been made in QCA. In this research, the goal is to focus on latency behavior and time domain (memory access time index) on memory, in this regard, the Heinsberg uncertainty principle method was used for approximate and quantitative estimation of time. The result shows that whatever Memory is larger in terms of area and number of cells, the delay will also be greater. Using QCAPro software, changes in energy dissipation during the read and write operation resulted in changing the input value from zero to one has a greater impact on latency. The result was that changing the input value from zero to one would have a greater impact on the latency. The delay was calculated in terms of clock cycle for each of the investigated structures. The design was performed using serial and parallel architectures in ۴ × ۱ and ۴ × ۴ dimensions, and the delay was more accurately investigated. The results indicated that in the parallel architecture, memory cell output (۲۶.۹۵%), memory cell loop (۲۲.۴۵%), decoder (۲۰.۵۲%), and ultimately read and write wire (۱۴.۹۴%) The order was the most delayed. In the series architecture, this includes the memory cell loop (۲۷.۵%), the memory cell output (۲۶.۵%), the reading wire (۱۱.۵%), writing wire (۵.۹%) and decoder (۸/۵%). In general, the area, the number of constituent cells, the amount of energy dissipation, and the change in the input value from zero to one, and the order of the components mentioned in the serial and parallel architecture, are factors affecting the latency (access time).