Abstarct: CMOS quadrature voltage controlled oscillators (QVCOs) have played prominent role in recent modern communication systems. They have been applied in different range of applications, such as zero-IF receivers, image rejection architectures, clock and data recovery (CDR), and QPSK modulators. Due to communication industry development, QVCOs with low-phase noise, low-power, high accuracy and high integration designs are required.To generate quadrature signals, several methods have been proposed so far. Among these methods, the LC-QVCOs have drawn lots of attentions because of their low-phase noise and better performance in high frequencies. In general, the LC-QVCOs are composed of two core LC-VCOs and a coupling network. Designing low-power and low-phase noise LC-VCOs with appropriate noiseless coupling network is a tremendous challenge. In this thesis, three high performance QVCO with low-power and low-phase noise are proposed. In all proposed methods, the coupling network is composed of low-noise and passive elements. Thus it could improve the phase noise and power of the circuits. The cores of the first proposed method is cross-connected LC-VCOs and injection has been done through the gates of the series transistors and circuit works at the supply voltage of 1.8 V. The second proposed circuit contains cross-connected LC-VCOs with Darlington cell which can enhance the transconductance of the circuit. In this method, injection has been done through the substrate.In comparison with first method the power consumption and phase noise improve. In the third proposed method a modified Colpitts has been used as a core of the QVCO which enhance the transconductance of the circuit and subsequently decrease the power consumption. Owing to the use of a class-C oscillator like Colpitts, the phase noise of the circuit is also improved. The power consumption is 2.88 mW at the supply voltage of 1.2 V and the phase noise of the QVCO at 1 MHz frequency offset from the 5.23 GHz is -122.8 dBc/Hz. Notably, all the proposed circuits have been simulate ADS in TSMC 0.18 μm RF-CMOS technology. Furthermore the third proposed QVCO is post-layout simulated by Cadence in single-well TSMC 0.18 μm RF-CMOS technology.