TK542 : Design and Simulation of Low-Phase Noise ILFD Using Class C Oscillators
Thesis > Central Library of Shahrood University > Electrical Engineering > MSc > 2016
Authors:
Abstarct: In recent years, wireless communications have played a key role in everyday lives of people. Today, demand for electronic devices dramatically increases at a low cost, low power consumption, high operating frequency etc.
Frequency synthesizer is one of the essential parts in transmitter and receiver systems. Frequency synthesizers have the ability to produce signals in the desired frequency range and are composed of parts such as frequency divider and mixer. In fact, one of the basic building blocks in frequency synthesizers is frequency divider that its divides input signal frequency to a desired devision factor. Frequency dividers are categorized into two groups: digital and analog. Conventional digital dividers are not suitable for division at high frequencies, because firstly they have a high power consumption, and secondly their performance at high frequencies are degrated. Therefore, analog dividers are used in high frequencies, which LC oscillator-baxsed injection locked frequency divider (ILFD) is one of the important analog dividers. LC-ILFDs have two advantages of relatively lower power consumption and higher operating frequency. Usually these dividers have the ability for frequency division on even and odd integer ratio.
So far, several methods have been proposed for division with ratios of two and three of which can refer to direct injection and indirect injection methods for dividing by two and series injection, parallel injection and direct injection methods for dividing by three.
In this thesis, two new frequency dividers are proposed through applying class-C oscillators like Colpitts, which have better phase noise. In the proposed methods, no additional elements for the injection have been used and in return, substrate and intermediate node of capacitors are used for injection. Thus the sources of noise and power consumption of the circuit is largely reduced.
Also, due to the lack of precise benchmark for the diagnosis of the divider locking, this thesis provides a new benchmark baxsed on eye diagrams to better identify the locking of ILFD.
In the first proposed circuit, injection has been done through the substrate that power consumption is equal to 2.69 mW at the supply voltage of 1.6 V. Also at power injection of 0 dBm, locking range of 3.78 GHz (22.11%) is achieved and phase noise of ILFD at 1-MHz frequency offset from 5.61 GHz is equal to -128.63 dBc/Hz. In the second proposed circuit, injection has been done via Colpitts capacitors which it’s power consumption is 2.49mW, locking range is between 5.7 GHz-10.56 GHz (23.21%) and phase noise divider at 1-MHz frequency offset from 5.61 GHz is equal to -128.69 dBc/Hz. Notably, all the proposed circuits have been simulated using ADS in TSMC 0.18μm RF-CMOS technology.
Keywords:
#Frequency synthesizer #Digital and Analog dividers #Injection-Locked Frequency Divider #Locking Injection
Keeping place: Central Library of Shahrood University
Visitor:
Keeping place: Central Library of Shahrood University
Visitor: