Abstarct: The phase-locked loop plays a key role in communication systems and is used in radio transceiver as frequency synthesizer. In most integrated circuit for control and communications, phase lock loop is used to synchronize input and output clock. Since the characteristic frequency of high frequency oscillators usually changes with variation of temperature and other parameters, In applications where frequency accuracy and stability are important the frequency synthesizer is utilized. The reference frequency in synthesizer is generated by a low frequency crystal oscillator with very low sensitivity therefore the output frequency of synthesizer which is multiple (integer or fraction) of the reference frequency is also very low sensitive. Usually pulse swallower and delta-sigma Modulators (DSM) are used for generating fractional division in a synthesizer loop. However the DSM produces quantization noise which create spurs around the main frequency. In this thesis a nested-PLL structure has been used that consists of a conventional PLL as a frequency multiplier (*M) in feedback path that make fraction M/N along divider (N) and in this way spurs caused by delta-sigma modulator are removed. The proposed synthesizer is simulated systematically in MATLAB Simulixnk and transistor level in ADS at 0.18µm CMOS technology. Also to verify the proposed structure a prototype of the synthesizer with Fref=100MHz and Fout=1GHz-1.3GHz is designed. The spurs of the proposed synthesizer at 1.2GHz center frequency are -220.15dBc and -216.22dBc at 143MHz and 162MHz offset frequency, respectively. In ADS simulation the duration of lock time for 8mv ripple at control voltage is less than 10µs.