Abstarct: The use of electronic systems in our lives is growing fast. With development at electronic systems, demands and is increased and new challenges in analog and digital integrated circuit design has been created. The possibility of using a combination of analog and digital circuits to implement a system on a single chip has many advantages such as decreasing costs and size of electronic devices. CMOS IC usually requires only a Poly-Si laxyer. In some special cases second laxyer is needed, for example to obtain linear capacitors (i.e. making PIP capacitor). This second laxyer causes increase in the cost and area. For solving these problems MOS varactor is suggested. MOS varactor can be made with single poly silicon laxyer and is controlled by tuning voltage. The main problem in conventional MOS varactors is their nonlinear behavior of their capaciance to tuning voltage that decreases the performance circuits. The narrow bands of linearity range lead to a fast slope in the capacity to voltage curve and increase sensitivity to noise. In this thesis a new MOS varactor configuration is proposed to decrease the nonlinearity and increase the linear range. In the proposed structure firstly the gate voltage for linear range is extracted. By applying the appropriate voltage to bulk of the varactor the threshold voltage can be changed and the C-V curve of the varactor is shifted. Using this idea and paralleling a certain number of varactors with different thereshold voltages (i.e. different bulk-source voltages), the linear parts of C-V curve of each varactor is added to the others and a vactor with wider C-V curve can be obtained. Finally baxsed on simulation results the linear voltage range has been increased from 0.3V in conventional structure to 0.9 V in the proposed configuration.