Abstarct: Wavelet transform is a useful tool for various applications in signal processing And in many fields such as audio and video processing, image noise reduction, pattern recognition, image coding and Compression is used. For this reason providing strategies for increasing the speed of implementation of wavelet transform is considered Which is one of the best strategies is the use of parallel processing and FPGA chips. A new and effective architecture has been proposed in this thesis for implementation of two dimensional discrete wavelet transform to compress images. In this research lifting schema approach has been used which is a newer and more efficient against filter banks approach, also the 5.3 wavelet filter has been used which is applied for lossless image compressing. The goal of this research is hardware tools complexity reduction, optimization of number of applied components and operation frequency increment. The new architecture consists of a processor unit for calculation of two dimensional discrete wavelet transform coefficients and one control unit for controlling of data flow in processor and producing the address buses of memory and one external memory for coefficients saving. This architecture has been simulated with VHDL hardware programing language and Xilinx Ise software which is one of the best and strongest software for FPGA programing. The obtained results has been evaluated and compared with other architecture. Two dimensional discrete wavelet transform with lifting schema approach has been simulated in MATLAB language and output images are compared in two environments.