Abstarct: Today, power management has become very significant in the electronics industry. The increasing development of portable devices powered by batteries such as cellular phones, laptops, etc. has made power management one of the most important concerns of the integrated circuit industry. Portable electronic devices require power management techniques to reduce power consumption and increase battery life. Due to the growing use of portable electronic devices and the rising tendency to decrease the volume and simultaneously increase the battery life used in this equipment, there is a need for regulators that are able to provide a constant and stable voltage for load from the minimum input voltage with the least losses. Among different types of regulators, low dropout (LDO) voltage regulators are the preferred choice for power management solutions due to their simplicity, fast response, and low implementation cost. Usually every LDO regulator needs a large external capacitor, in the range of a few microfarads, to function properly. These external capacitors take up a lot of space, increase the number of IC pins, and make it impossible to implement system on a chip (SoC). In addition, the correct performance of the compensation through the external capacitor is strongly dependent on the equivalent series resistant (ESR). As a result of such limitations, researchers seek to completely eliminate the external capacitor while maintaining the desired voltage regulator characteristics. Research has been done to remove the external capacitor, including the use of capacitance multiplier, pole splitting technique, and so on. These compensation methods usually use an internal capacitor to compensate. Maintaining the desired characteristics of the voltage regulator and simultaneously providing stability with a smaller capacitor would be considered as an innovation and progress. This dissertation presents a method for removing a large external capacitor from the structure of conventional LDO voltage regulators. This enables an integrated system for SoC applications. In this work, a new frequency compensation method baxsed on lead compensation is presented, which provides full ac frequency stability for zero to 50 mA load current. This voltage regulator without external capacitor is designed and simulated with standard 0.18u TSMC technology in Cadence software. The simulation results show that the regulator produces a constant output voltage of 1.6V with an output current of zero to 50mA with a voltage dropout of 200mV,has characteristic figure of merit 25fs, line regulation 0.11mV/V and load regulation 0.00092mV/mA with PSR equal -59dB which consumes only 90uA of quiescent current.