Abstarct: Operation Amplifiers (Op-Amp) are the main building block in analog circuits. OAs have different structures for different applications. With the advances in technology and reducing the power supply voltage, the need to use the entire power supply range at both input and output of amplifiers have increased. Rail-to-rail amplifiers were proposed to address these new needs. The biggest challenge with traditional rail-to-rail amplifiers, (implemented with an NMOS and PMOS differential pair), is the input transconductance (gm) variation. These variations have significant effects on amplifier performance such as gain, stability, bandwidth and linearity. In this study, a new structure for the input stage of Rail-to-Rail amplifiers has been proposed. The proposed structure reduces input stage gm variation by 13 percent. This structure uses four input pairs, which reduces input stage gm variation by changing the input voltage range of the two pairs. This compensates for the non-overlapping areas by the other two pairs. To change the voltage range, a diode connection structure is used in the tail current path. The proposed amplifier is simulated in Cadence environment using 180nm CMOS technology in 1.8V power supply. The proposed amplifier drives a capacitive load of 10pF and achieves a DC gain of 103.9dB, unity gain bandwidth (GBW) of 3.1MHz, and Slew rate 0.33V/µs, while consuming 20µW of power.