Abstarct: Due to the growing demand for battery-powered electronic equipment, the need for regulators with constant and stable output voltage is strongly felt. Another point to note is that the regulator used in this equipment must have a small voltage drop to be implemented in new technologies with low power supplies.Among these regulators, regulators known as LDO are one of the best options for use in circuits in this equipment.These regulators are often used in noise-sensitive analog circuits such as analog-to-digital converters and mixers. In some cases, sequential switching of digital circuits causes fluctuations in the supply voltage, which due to the said sensitivity, the presence of these voltage changes has an adverse effect on the circuits.The regulator’s ability to eliminate fluctuations in the supply voltage is called PSR. In this thesis, a new architecture for improving PSR in a low drop-out voltage regulator is presented. In this architecture, creating a leading path from the power supply to the pass transistor gate causes the gate-source voltage changes of the transistor to be constant due to fluctuations in the supply voltage, which results in improved PSR at the output of the voltage regulator. Also, by using a frequency compensation method, the amount of Voltage undershoot and overshoot is reduced compared to the sudden change of current. In addition, due to the reduction of the nondominant pole effect due to the zero created in the path of the voltage regulator transfer function, the circuit can reach the 70 ° phase margin without the need for an on-chip capacitor. Due to the fact that reducing the power consumption as much as possible increases the life of batteries, so we have tried to minimize the power consumption by biasing the circuit transistors in the subthreshold region and also using the current reuse technic. The proposed regulator is designed and simulated in Cadence software with TSMC 180nm CMOS technology for an output voltage of 1.6 V and a load current of 50 μA to 50 mA. The Monte Carlo simulation results show the output voltage, rate of change 860 μV with a standard deviation of 125 μV. The proposed circuit with an active area of 1.46 mm2 and the input voltage of 1.8 to 2 volts and power consumption of only 5.4 microwatts has a line regulation of 0.142 mAµV , a load regulation of 5.12 mAµV and a PSR equal to -80 dB at a frequency of 1 kHz.