TK834 : Design and simulation of a sub-1V nano-watt comparator and its optimization using evolutionary algorithms
Thesis > Central Library of Shahrood University > Electrical Engineering > MSc > 2021
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Abstarct: Today, with the increase in the efficiency of digital signal processors in data processing, the use of analog-to-digital converters has increased. Design to achieve very low power, smaller area and high speed in analog to digital converters are the design challenges of comparators. Also with the advancement of technology and the use of digital circuits, reducing the amount of power supply is another important point. Reducing the power supply has serious effects on circuit performance, so it is important to use a circuit that can function properly. Also today, with the downsizing of electronic circuits, reducing power consumption is another challenge of comparator design. Optimization methods can be used to improve the efficiency of electronic circuits. Nowadays, optimization methods using evolutionary algorithms have many applications in integrated circuits. In the general structure of these algorithms, the variables that the purpose of the design is to optimize are considered as objective functions and will try to improve the objective function by repeating the simulation.
In this research, we present a comparator with a power consumption of about nano watts with an input voltage below one volt. In the proposed structure, we applied the input to the bulk and connected the gate of the input transistors to the ground and used the transconductance of the transistor’s body. The proposed comparator is designed using HSPICE software in 0.18 µm CMOS technology with 0.6 V power supply. Also, the power of the proposed comparator is about 34 nanowatts. Due to the existence of many parameters in the comparator, it is very important to provide a functionally optimal comparator. As mentioned, one of the methods used in optimizing integrated circuits is the use of evolutionary algorithms. In this research, we also considered the comparator delay time as the objective function and presented the proposed comparator using particle swarm algorithm. Using the particle swarm algorithm, the comparator delay time was improved by 25% and the power consumption by 12%.
Keywords:
#optimization #sub-1 voltage comparator #0.18 µm CMOS technology Keeping place: Central Library of Shahrood University
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