Abstarct: Because of the specific features of pipelined ADCs such as medium-high resolution from 8 to 16 bits, low power consumption (Pdiss), high speed and sampling rates (fs) ranging from a few MS/s to hundreds of MS/s so, they are widely used in many handheld commercial (mobile phone), industrial, military and communication applications. Since operational transconductance amplifier (OTA) is one of the main blocks of the ADCs and imposes the high power dissipation to these blocks, several techniques have been proposed to reduce the power dissipation of ADCs. In this dissertation, the first goal is decreasing the power consumption by eliminating the OTA in current charge pump (CCP) technique. The second goal is to improve the other crucial specification like accuracy, so in order to achieve high accuracy, a variable current source (VCS) is implemented. The third goal is a suitable speed which can be used in different applications. To achieve this goal, the differential-multi-level-variable-current-source (DML-VCS-CCP) is introduced. Having a high accuracy and speed, the proposed DML-VCS-CCP structure can be a suitable choice for different applications With the aid of the proposed technique, a pipelined ADC with the sampling frequency of 2.5MHz, 10-bit resolution, with 1.8 V supply voltage is designed and simulated. The simulation of this structure is done by the HSPICE-2008 software. The results show that the designed ADC has achieves 50 dB SNDR and its ENOB is 8 bits, while it is consuming 38.2 mW.