Abstarct: Operational transconductance amplifiers (Gm Cells) are one of the main building blocks in analog integrated circuits, such as Gm-C filters, VCOs and analog multipliers. They have different advantages such as good performance in high frequency applications, low power consumption, simple tunning and implementation. However they suffer from nonlinearity. Therefore, in this thesis, a new method for increasing the input linearity range of Gm-Cells is presented. The main purpose of the proposed circuit is reduction of harmonic frequency components. The proposed circuit consists of combination of two parallel fully differential pairs which their input-output Characteristics are shifted and added together. Since the current of a MOS transistor depends on the threshold voltage which is affected by the transistor bulk voltage, in this thesis first the required shift is created by applying a certain voltage to the subatracte. The proposed circuit is simulated in ADS using TSMC 0.18µm CMOS thechnology. Sourse degeneration method is also used to achieve more linearity improvement. Finally the two mentioned cells are parallelled to a symmetric cell for further increase in the linearity range. The transconductance gain in the proposed structure is 74µA/V and the linearity range of the input voltage is 0.8Vpp. THD and HD3 parameters (for 0.8Vpp differential input at 10MHz frequency) are -62dB and -69dB respectively. It is necessary to mention that the total power consumption at 1.8v supply voltage and 0.9V output common mode voltage, is 260µW.