TK324 : Design, Simulation and Hardware Implementation of a Real-Time Video Compression Algorithm baxsed on FPGA
Thesis > Central Library of Shahrood University > Electrical Engineering > MSc > 2013
Authors:
Abstarct: Today, the growing need to transmit and store information makes data compression an important issue. Variety of video data are increasingly produced, stored and transmitted in different application that make an important role in everyday life, exploration applications, space industry and military industry. In many of these applications real-time video streaming and storage is required. In real-time application, processing speed is critical issue, because high volume of input data needs to be compressed in real-time. Furthermore, the flexibility and the ability to update the system with low cost are also highly regarded. One of the best ways to increasing the speed is parallel processing. An appropriate strategy to achieve parallel processing is using FPGAs for their Parallelization capabilities and high flexibility. Parallelization ability is an appropriate strategy for increasing processing speed; high performance and speed are achievable with an appropriate design. In this thesis, we propose a method for real-time compressing in FPGA-baxsed hardware.
In this regard, a low-complexity high parallelism block-baxsed wavelet video compression algorithm with appropriate hardware compatibility, which has extracted from block compression algorithms such as EBCOT and SBHP, is purposed and designed. Then we design a hardware baxsed on software needs. At the end, execution time and speed are compared with similar works. Result shows optimization in terms of use of available hardware resources compare with two other methods.
Keywords:
#real time video compression – parallelization – wavelet transform – lifting scheme - FPGA Link
Keeping place: Central Library of Shahrood University
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Keeping place: Central Library of Shahrood University
Visitor: