Abstarct: Analog switched-capacitor circuits are an important category of analog circuits, with one of their key applications being in sample-and-hold circuits. To reduce supply voltage and power consumption, MOS transistors have been scaled down. However, reducing the size leads to significant challenges, the most critical of which is the increase in leakage current in the off state. To address this issue, researchers have sought suitable alternatives to MOS transistors. Carbon nanotube transistors (CNTFETs) allow for the use of a thicker dielectric in the gate because their threshold voltage is not dependent on the gate oxide thickness, thereby reducing gate leakage current without increasing the threshold voltage. In this thesis, a new sample-and-hold circuit is proposed. The advantage of the proposed circuit is that the operational amplifier is activated by a clock pulse during the hold phase and is turned off during the sampling phase, resulting in a significant reduction in power consumption. The circuit uses transmission gates, bootstrapped switches, and dummy switches, which minimizes the charge injected into the load capacitor, thereby increasing the circuit’s accuracy. To simulate and verify the performance of the proposed circuit, the HSPICE simulator was used, and the transistors were modeled using 32nm CNT technology. The simulation results of the proposed sample-and-hold circuit demonstrate that it can achieve an accuracy of over 14 bits at an input frequency of 218.75 MHz and a sampling frequency of 2 GHz, with a peak-to-peak voltage swing of 0.4V. Meanwhile, the circuit operates with a supply voltage of 1V and consumes 168 µW of power.