Abstarct: In image processing filters play an essential role in the elimination of random noises such as the salt and pepper noise and the noise produced by the shaking of hands when photographing, or noises caused by the lack of light in the image. The main problem faced when filtering an image is multiplication which cause the drop in speed. If implemention of filter on hardware such as FPGA is intended, multiplication will occupy a large space and if poly - multipliers are required then it would lead to complications. This project aims to replace the space consuming and speed dropping multiplication method with the adding and shifting technique which increases the speed of signal filtration. This is achievable by employing binary methods. However, a method called «Canonical Sign Digit» in which the number of non-zero digits are considerably reduced and is therefore a more suitable solution. This method has been previously employed on the FIR filter and has resulted not only in the improvement of the filtration speed but has enabled use of higher level filters as well. The present research attempts to implement a method baxsed on «Canonical Sign Digit». It is implemented on a two-dimensional filter with an accuracy of between8 to 20 bits and the findings recorded and compared with the employment of the same filter in binary formation. The reduction of the collectors in the proposed method in comparison to the binary method is found to be highly significant and errors in the proposed method are minimal in comparison to the pre-prepared MATLAB command. If we assume the required bits for the filter multipliers as 12 bits, 84 adders will be required in the proposed method while the same figure for the binary method would be 286 adders and the similarity rate between our method and the pre-prepared MATLAB command is %93.